Finished and turned in the mid semester project report which detailed that our current problem is getting our pcb design approved, programming our board and creating our own bareduino. Something we didn't take into effect is that on our PCB design we didn't do a DRC check, upon checking on our errors we realized that the design has 41 errors. Most errors are tiny airwaves within the parts which comes from changing between measurements while connecting the wires.

The meeting with connect was postponed to Saturday and as such, we moved our lab hours to accommodate his presence.

Informed Kenneth about the design: - The design had changed GND_T to GND

Changed the clock from 8Mhz to 16Mhz Must have new traces/signals on the header for the FTDI since the original design was meant to run off of the same voltage as a battery.